Integrated circuits (ICs) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from a semiconductor substrate. Multiple levels of metal interconnect wiring above the semiconductor portion of the substrate are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the semiconductor substrate and conductive vias run perpendicular to the semiconductor substrate. The conductive vias typically interconnect the different levels of the metal wiring levels.
Two developments in the last decade have contributed to increased performance of contemporary ICs. One such development is the use of copper as the interconnect metal of the BEOL interconnect structure. Copper is advantageous because it has a higher conductivity compared with the other traditionally used interconnect metals, such as, for example, aluminum (Al). A second development is the employment within the BEOL interconnect structure of a low dielectric constant (low k) dielectric material as the interlayer dielectric (ILD) layer or layers. By “low k,” it is meant that the dielectric constant of a particular dielectric material is less than that of silicon dioxide (SiO2). When copper is used as the metal in the interconnect wiring layers, a barrier layer is typically required between the copper lines and the ILD layer to prevent copper from diffusing into the ILD material and damaging the electrical properties of the ILD layer.
One recently developed approach for fabricating copper interconnections involves forming copper lines by subtractively patterning a copper layer that overlies a dielectric layer on a substrate using an etching process. Portions of the dielectric layer that are laterally adjacent to the copper lines become exposed during the subtractive etching of the copper layer. A tantalum nitride (TaN) barrier layer is then uniformly deposited overlying the copper lines and the exposed portions of the dielectric layer. To eliminate electrical shorting between the copper lines, portions of the TaN barrier layer disposed between the copper lines are removed using a reaction ion etching (RIE) process. An ILD layer is then deposited overlying the copper lines and adjacent portions of the dielectric layer. Unfortunately, the RIE etching process is relatively aggressive and can also partially remove and/or damage portions of the TaN barrier layer that overlie the copper lines including, in particular, along the sidewalls of the copper lines. As such, these remaining portions of the TaN barrier layer may be too thin or damaged to prevent copper from the copper lines from diffusing into the ILD layer.
Accordingly, it is desirable to provide integrated circuits including copper lines and diffusion barriers that inhibit copper from the copper lines from diffusing into an ILD layer and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.